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IPPS
2002
IEEE
16 years 3 days ago
Variable Partitioning and Scheduling of Multiple Memory Architectures for DSP
Multiple memory module architecture enjoys higher memory access bandwidth and thus higher performance. Two key problems in gaining high performance in this kind of architecture ar...
Qingfeng Zhuge, Bin Xiao, Edwin Hsing-Mean Sha
ISORC
2000
IEEE
15 years 11 months ago
Hybrid Sequence Charts
We introduce Hybrid Sequence Charts (HySCs) as a visual description technique for communication in hybrid system models. To that end, we adapt a subset of the well-known MSC synta...
Radu Grosu, Ingolf Krüger, Thomas Stauner
VTS
1996
IEEE
112views Hardware» more  VTS 1996»
15 years 11 months ago
Optimal voltage testing for physically-based faults
In this paper we investigate optimal voltage testing approaches for physically-based faults in CMOS circuits. We describe the general nature of the problem and then focus on two f...
Yuyun Liao, D. M. H. Walker
ACSD
2003
IEEE
105views Hardware» more  ACSD 2003»
15 years 11 months ago
Detecting State Coding Conflicts in STG Unfoldings Using SAT
Abstract. The behaviour of asynchronous circuits is often described by Signal Transition Graphs (STGs), which are Petri nets whose transitions are interpreted as rising and falling...
Victor Khomenko, Maciej Koutny, Alexandre Yakovlev
EUROCOLT
1995
Springer
15 years 10 months ago
A decision-theoretic generalization of on-line learning and an application to boosting
k. The model we study can be interpreted as a broad, abstract extension of the well-studied on-line prediction model to a general decision-theoretic setting. We show that the multi...
Yoav Freund, Robert E. Schapire