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FOCS
2002
IEEE
16 years 7 days ago
Load Balancing with Memory
A standard load balancing model considers placing Ò balls into Ò bins by choosing possible locations for each ball independently and uniformly at random and sequentially placing...
Michael Mitzenmacher, Balaji Prabhakar, Devavrat S...
MICRO
2002
IEEE
104views Hardware» more  MICRO 2002»
16 years 6 days ago
Reducing register ports for higher speed and lower energy
The key issues for register file design in high-performance processors are access time and energy. While previous work has focused on reducing the number of registers, we propose...
Il Park, Michael D. Powell, T. N. Vijaykumar
ISCA
2010
IEEE
199views Hardware» more  ISCA 2010»
16 years 3 days ago
A case for FAME: FPGA architecture model execution
Given the multicore microprocessor revolution, we argue that the architecture research community needs a dramatic increase in simulation capacity. We believe FPGA Architecture Mod...
Zhangxi Tan, Andrew Waterman, Henry Cook, Sarah Bi...
ICALP
2010
Springer
16 years 2 days ago
On the Relation between Polynomial Identity Testing and Finding Variable Disjoint Factors
We say that a polynomial f(x1, . . . , xn) is indecomposable if it cannot be written as a product of two polynomials that are defined over disjoint sets of variables. The polynom...
Amir Shpilka, Ilya Volkovich
GI
2009
Springer
15 years 12 months ago
Challenges of Electronic CAD in the Nano Scale Era
: Future nano scale devices will expose different characteristics than todays silicon devices. While the exponential growth of non recurring expenses (NRE, mostly due to mask sets)...
Christian Hochberger, Andreas Koch
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