2449 search results - page 338 / 490 » VLSI |
145
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ISVLSI
2003
IEEE
16 years 7 days ago
2003
IEEE
Previous work has shown that cache line sizes impact performance differently for different desktop programs – some programs work better with small line sizes, others with larger...
124
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ITC
2003
IEEE
16 years 7 days ago
2003
IEEE
This paper deals with Hybrid multisite testing of VLSI chips by utilizing automatic test equipment (ATE) in connection with built-in self-test (BIST). The performance of a multisi...
170
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VLSID
2003
IEEE
16 years 7 days ago
2003
IEEE
With the emergence of the packet-switched networks as a possible system-on-chip (SoC) communication paradigm, the design of network-on-chips (NoC) has provided a challenge to the ...
149
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SBCCI
2003
ACM
16 years 6 days ago
2003
ACM
Networks-on-Chip (NoCs) interconnection architectures to be used in future billion-transistor Systems-on-Chip (SoCs) meet the major communication requirements of these systems, of...
172
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SBCCI
2003
ACM
16 years 6 days ago
2003
ACM
– We present a new architecture for signed multiplication which maintains the pure form of an array multiplier, exhibiting a much lower overhead than the Booth architecture. This...