1399 search results - page 164 / 280 » Verification of Test Suites |
181
click to vote
ICSE
2010
IEEE-ACM
15 years 8 months ago
2010
IEEE-ACM
Typestate analysis determines whether a program violates a set of finite-state properties. Because the typestate-analysis problem is statically undecidable, researchers have propo...
197
click to vote
DAC
2008
ACM
2008
ACM
Model checking based analysis of end-to-end latency in embedded, real-time systems with clock drifts
16 years 7 months ago
End-to-end latency of messages is an important design parameter that needs to be within specified bounds for the correct functioning of distributed real-time control systems. In t...
164
click to vote
DAC
2005
ACM
16 years 7 months ago
2005
ACM
We present an efficient search strategy for satisfiability checking on circuits represented at the register-transfer-level (RTL). We use the RTL circuit structure by extending con...
161
click to vote
DAC
2005
ACM
16 years 7 months ago
2005
ACM
Recent study shows that the existing first order canonical timing model is not sufficient to represent the dependency of the gate delay on the variation sources when processing an...
185
click to vote
SIGSOFT
2005
ACM
16 years 7 months ago
2005
ACM
We present a context- and path-sensitive algorithm for detecting memory leaks in programs with explicit memory management. Our leak detection algorithm is based on an underlying e...