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CHARME
2005
Springer
94views Hardware» more  CHARME 2005»
15 years 12 months ago
Verifying Quantitative Properties Using Bound Functions
Abstract. We define and study a quantitative generalization of the traditional boolean framework of model-based specification and verification. In our setting, propositions have...
Arindam Chakrabarti, Krishnendu Chatterjee, Thomas...
142
Voted
FMCAD
2000
Springer
15 years 10 months ago
Model Checking Synchronous Timing Diagrams
Abstract. Model checking is an automated approach to the formal verification of hardware and software. To allow model checking tools to be used by the hardware or software designer...
Nina Amla, E. Allen Emerson, Robert P. Kurshan, Ke...
173
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MEMOCODE
2007
IEEE
16 years 19 days ago
Towards Equivalence Checking Between TLM and RTL Models
The always increasing complexity of digital system is overcome in design flows based on Transaction Level Modeling (TLM) by designing and verifying the system at difbstraction le...
Nicola Bombieri, Franco Fummi, Graziano Pravadelli...
158
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DATE
2004
IEEE
129views Hardware» more  DATE 2004»
15 years 10 months ago
On the Design and Verification Methodology of the Look-Aside Interface
In this paper, we present a technique to design and verify the Look-Aside (LA-1) Interface standard used in network processors. Our design flow includes several refinements starti...
Ali Habibi, Asif Iqbal Ahmed, Otmane Aït Moha...
195
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TABLEAUX
2007
Springer
16 years 14 days ago
Bounded Model Checking with Description Logic Reasoning
Abstract. Model checking is a technique for verifying that a finite-state concurrent system is correct with respect to its specification. In bounded model checking (BMC), the sys...
Shoham Ben-David, Richard J. Trefler, Grant E. Wed...