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NIXDORF
1992
116views Hardware» more  NIXDORF 1992»
15 years 11 months ago
Programmable Active Memories: A Performance Assessment
We present some quantitative performance measurements for the computing power of Programmable Active Memories (PAM), as introduced by [2]. Based on Field Programmable Gate Array (...
Patrice Bertin, Didier Roncin, Jean Vuillemin
DAC
2010
ACM
15 years 11 months ago
A parallel integer programming approach to global routing
We propose a parallel global routing algorithm that concurrently processes routing subproblems corresponding to rectangular subregions covering the chip area. The algorithm uses a...
Tai-Hsuan Wu, Azadeh Davoodi, Jeffrey T. Linderoth
GLVLSI
2007
IEEE
194views VLSI» more  GLVLSI 2007»
15 years 11 months ago
Probabilistic maximum error modeling for unreliable logic circuits
Reliability modeling and evaluation is expected to be one of the major issues in emerging nano-devices and beyond 22nm CMOS. Such devices would have inherent propensity for gate f...
Karthikeyan Lingasubramanian, Sanjukta Bhanja
CCS
2006
ACM
15 years 11 months ago
Safety and consistency in policy-based authorization systems
In trust negotiation and other distributed proving systems, networked entities cooperate to form proofs that are justified by collections of certified attributes. These attributes...
Adam J. Lee, Marianne Winslett
DSN
2004
IEEE
15 years 11 months ago
The Recursive NanoBox Processor Grid: A Reliable System Architecture for Unreliable Nanotechnology Devices
Advanced molecular nanotechnology devices are expected to have exceedingly high transient fault rates and large numbers of inherent device defects compared to conventional CMOS de...
A. J. KleinOsowski, Kevin KleinOsowski, Vijay Rang...
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