85 search results - page 7 / 17 » Wrong-path Instruction Prefetching |
203
Voted
ICS
2007
Tsinghua U.
16 years 16 days ago
2007
Tsinghua U.
Software or hardware data cache prefetching is an efficient way to hide cache miss latency. However effectiveness of the issued prefetches have to be monitored in order to maximi...
160
Voted
IPPS
2003
IEEE
15 years 11 months ago
2003
IEEE
Concurrent multithreaded architectures exploit both instruction-level and thread-level parallelism through a combination of branch prediction and thread-level control speculation. ...
128
Voted
MICRO
2008
IEEE
16 years 23 days ago
2008
IEEE
—L1 instruction-cache misses pose a critical performance bottleneck in commercial server workloads. Cache access latency constraints preclude L1 instruction caches large enough t...
179
Voted
ISCA
1995
IEEE
15 years 10 months ago
1995
IEEE
Current trends in processor design are pointing to deeper and wider pipelines and superscalar architectures. The efficient use of these resources requires speculative execution, ...
154
Voted
CC
2007
Springer
16 years 17 days ago
2007
Springer
Reference counting is a classical garbage collection method. Recently, a series of papers have extended the basic method to drastically reduce its notorious overhead and extend the...