1000 search results - page 100 / 200 » Yield-Aware Cache Architectures |
152
click to vote
ICCD
2005
IEEE
16 years 3 months ago
2005
IEEE
As technology scales, interconnects dominate the performance and power behavior of deep submicron designs. Three-dimensional integrated circuits (3D ICs) have been proposed as a w...
165
click to vote
ICCD
2007
IEEE
16 years 1 months ago
2007
IEEE
Leakage power has grown significantly and is a major challenge in microprocessor design. Leakage is the dominant power component in second-level (L2) caches. This paper presents t...
154
click to vote
MICRO
2006
IEEE
16 years 22 days ago
2006
IEEE
With the trend towards increasing number of processor cores in future chip architectures, scalable directory-based protocols for maintaining cache coherence will be needed. Howeve...
189
click to vote
SKG
2006
IEEE
16 years 22 days ago
2006
IEEE
The simplicity and robustness of unstructured P2P system make it a preferable architecture for constructing real large scale file sharing system. Most of the existing paradigms re...
200
click to vote
WMPI
2004
ACM
16 years 4 days ago
2004
ACM
The size and speed of first-level caches and SRAMs of embedded processors continue to increase in response to demands for higher performance. In power-sensitive devices like PDAs a...