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ISCA
2010
IEEE
205views Hardware» more  ISCA 2010»
16 years 12 days ago
The virtual write queue: coordinating DRAM and last-level cache policies
In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU’s data needs, and...
Jeffrey Stuecheli, Dimitris Kaseridis, David Daly,...
ACMSE
2006
ACM
15 years 11 months ago
Achieving efficient polynomial multiplication in fermat fields using the fast Fourier transform
We introduce an efficient way of performing polynomial multiplication in a class of finite fields GF(pm ) in the frequency domain. The Fast Fourier Transform (FFT) based frequency...
Selçuk Baktir, Berk Sunar
AI50
2006
15 years 11 months ago
The Physical Symbol System Hypothesis: Status and Prospects
I analyze some of the attacks against the Physical Symbol System Hypothesis--attacks based on the presumed need for symbolgrounding and non-symbolic processing for intelligent beha...
Nils J. Nilsson
ANCS
2006
ACM
15 years 11 months ago
Packet classification using coarse-grained tuple spaces
While the problem of high performance packet classification has received a great deal of attention in recent years, the research community has yet to develop algorithmic methods t...
Haoyu Song, Jonathan S. Turner, Sarang Dharmapurik...
APGV
2006
ACM
144views Visualization» more  APGV 2006»
15 years 11 months ago
Efficient selective rendering of participating media
Realistic image synthesis is the process of computing photorealistic images which are perceptually and measurably indistinguishable from real-world images. In order to obtain high...
Oscar Anson, Veronica Sundstedt, Diego Gutierrez, ...
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