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HPCA
2011
IEEE
14 years 11 months ago
ACCESS: Smart scheduling for asymmetric cache CMPs
In current Chip-multiprocessors (CMPs), a significant portion of the die is consumed by the last-level cache. Until recently, the balance of cache and core space has been primari...
Xiaowei Jiang, Asit K. Mishra, Li Zhao, Ravishanka...
ISCA
2006
IEEE
137views Hardware» more  ISCA 2006»
16 years 1 months ago
Multiple Instruction Stream Processor
Microprocessor design is undergoing a major paradigm shift towards multi-core designs, in anticipation that future performance gains will come from exploiting threadlevel parallel...
Richard A. Hankins, Gautham N. Chinya, Jamison D. ...
CORR
2006
Springer
108views Education» more  CORR 2006»
15 years 7 months ago
Two polygraphic presentations of Petri nets
: This document gives an algebraic and two polygraphic translations of Petri nets, all three providing an easier way to describe reductions and to identify some of them. The first ...
Yves Guiraud
CEE
2007
107views more  CEE 2007»
15 years 7 months ago
A non-preemptive scheduling algorithm for soft real-time systems
Real-time systems are often designed using preemptive scheduling and worst-case execution time estimates to guarantee the execution of high priority tasks. There is, however, an i...
Wenming Li, Krishna M. Kavi, Robert Akl
CISSE
2008
Springer
15 years 9 months ago
IraqComm and FlexTrans: A Speech Translation System and Flexible Framework
SRI International's IraqComm system performs bidirectional speech-to-speech machine translation between English and Iraqi Arabic in the domains of force protection, municipal ...
Michael W. Frandsen, Susanne Riehemann, Kristin Pr...
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