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DDECS
2007
IEEE
105views Hardware» more  DDECS 2007»
16 years 1 months ago
A Heuristic for Concurrent SOC Test Scheduling with Compression and Sharing
1-The increasing cost for System-on-Chip (SOC) testing is mainly due to the huge test data volumes that lead to long test application time and require large automatic test equipmen...
Anders Larsson, Erik Larsson, Petru Eles, Zebo Pen...
DDECS
2007
IEEE
93views Hardware» more  DDECS 2007»
16 years 1 months ago
Manifestation of Precharge Faults in High Speed DRAM Devices
Abstract: High speed DRAMs today suffer from an increased sensitivity to interference and noise problems. Signal integrity issues, caused by bit line and word line coupling, result...
Zaid Al-Ars, Said Hamdioui, Georgi Gaydadjiev
DFT
2007
IEEE
103views VLSI» more  DFT 2007»
16 years 1 months ago
Reliable Network-on-Chip Using a Low Cost Unequal Error Protection Code
The network-on-chip (NoC) paradigm is seen as a way of facilitating the integration of a large number of computational and storage blocks on a chip to meet several performance and...
Avijit Dutta, Nur A. Touba
DSN
2007
IEEE
16 years 1 months ago
Web Services Wind Tunnel: On Performance Testing Large-Scale Stateful Web Services
New versions of existing large-scale web services such as Passport.com© have to go through rigorous performance evaluations in order to ensure a high degree of availability. Perf...
Marcelo De Barros, Jing Shiau, Chen Shang, Kenton ...
DSN
2007
IEEE
16 years 1 months ago
SLAM: Sleep-Wake Aware Local Monitoring in Sensor Networks
Sleep-wake protocols are critical in sensor networks to ensure long-lived operation. However, an open problem is how to develop efficient mechanisms that can be incorporated with ...
Issa Khalil, Saurabh Bagchi, Ness B. Shroff