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1998
Springer
15 years 12 months ago
The Relation Between the Product Line Development Entry Points and Reengineering
The product line for software systems (PL) approach has been touted recently as one of the most promising development approach for gains in product quality, time to market and cost...
Jean-Marc DeBaud, Jean-Francois Girard
ISPD
1998
ACM
97views Hardware» more  ISPD 1998»
15 years 12 months ago
Device-level early floorplanning algorithms for RF circuits
—High-frequency circuits are notoriously difficult to lay out because of the tight coupling between device-level placement and wiring. Given that successful electrical performan...
Mehmet Aktuna, Rob A. Rutenbar, L. Richard Carley
ISPD
1998
ACM
79views Hardware» more  ISPD 1998»
15 years 12 months ago
On wirelength estimations for row-based placement
Wirelength estimation in VLSI layout is fundamental to any pre-detailed routing estimate of timing or routability. In this paper, we develop e cient wirelength estimation techniqu...
Andrew E. Caldwell, Andrew B. Kahng, Stefanus Mant...
ISPD
1998
ACM
99views Hardware» more  ISPD 1998»
15 years 12 months ago
CHDStd - application support for reusable hierarchical interconnect timing views
This paper describes an important new facility for timing-driven design applications within the new CHDStd standard for a SEMATECH design system for large complex chips. We first ...
S. Grout, G. Ledenbach, R. G. Bushroe, P. Fisher, ...
ISPD
1998
ACM
101views Hardware» more  ISPD 1998»
15 years 12 months ago
Greedy wire-sizing is linear time
—The greedy wire-sizing algorithm (GWSA) has been experimentally shown to be very efficient, but no mathematical analysis on its convergence rate has ever been reported. In this...
Chris C. N. Chu, D. F. Wong
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