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ICECCS
2010
IEEE
196views Hardware» more  ICECCS 2010»
15 years 7 months ago
Implementing and Evaluating a Model Checker for Transactional Memory Systems
Abstract—Transactional Memory (TM) is a promising technique that addresses the difficulty of parallel programming. Since TM takes responsibility for all concurrency control, TM ...
Woongki Baek, Nathan Grasso Bronson, Christos Kozy...
ICECCS
2010
IEEE
219views Hardware» more  ICECCS 2010»
15 years 7 months ago
Comparison of Six Ways to Extend the Scope of Cheddar to AADL v2 with Osate
Abstract—Cheddar is a framework dedicated to the specification of real-time schedulers, and to their analysis by simulation. It is developed in Ada. Some parts of its modular ar...
Mickaël Kerboeuf, Alain Plantec, Frank Singho...
ERCIMDL
2010
Springer
132views Education» more  ERCIMDL 2010»
15 years 7 months ago
A Visual Digital Library Approach for Time-Oriented Scientific Primary Data
Abstract. Digital Library support for textual and certain types of nontextual documents has significantly advanced over the last years. While Digital Library support implies many a...
Jürgen Bernard, Jan Brase, Dieter W. Fellner,...
ESORICS
2010
Springer
15 years 7 months ago
D(e|i)aling with VoIP: Robust Prevention of DIAL Attacks
We carry out attacks using Internet services that aim to keep telephone devices busy, hindering legitimate callers from gaining access. We use the term DIAL (Digitally Initiated A...
Alexandros Kapravelos, Iasonas Polakis, Elias Atha...
EUROPAR
2010
Springer
15 years 7 months ago
Optimized On-Chip-Pipelined Mergesort on the Cell/B.E
Abstract. Limited bandwidth to off-chip main memory is a performance bottleneck in chip multiprocessors for streaming computations, such as Cell/B.E., and this will become even mor...
Rikard Hultén, Christoph W. Kessler, Jö...
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