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ISCA
1995
IEEE
147views Hardware» more  ISCA 1995»
15 years 10 months ago
Dynamic Self-Invalidation: Reducing Coherence Overhead in Shared-Memory Multiprocessors
This paper introduces dynamic self-invalidation (DSI), a new technique for reducing cache coherence overhead in shared-memory multiprocessors. DSI eliminates invalidation messages...
Alvin R. Lebeck, David A. Wood
ISCA
1995
IEEE
133views Hardware» more  ISCA 1995»
15 years 10 months ago
Performance Evaluation of the PowerPC 620 Microarchitecture
The PowerPC 620TM microprocessor1 is the most recent and performance leading member of the PowerPCTM family. The 64-bit PowerPC 620 microprocessor employs a two-phase branch predi...
Trung A. Diep, Christopher Nelson, John Paul Shen
ISCA
1995
IEEE
118views Hardware» more  ISCA 1995»
15 years 10 months ago
The EM-X Parallel Computer: Architecture and Basic Performance
Latency tolerance is essential in achieving high performance on parallel computers for remote function calls and fine-grained remote memory accesses. EM-X supports interprocessor ...
Yuetsu Kodama, Hirohumi Sakane, Mitsuhisa Sato, Ha...
ISCAS
1995
IEEE
91views Hardware» more  ISCAS 1995»
15 years 10 months ago
An FPGA Based Reconfigurable Coprocessor Board Utilizing a Mathematics of Arrays
Abstract -- Work in progress at the University of Missouri-Rolla on hardware assists for high performance computing is presented. This research consists of a novel field programmab...
W. Eatherton, J. Kelly, T. Schiefelbein, H. Pottin...
ISCAS
1995
IEEE
97views Hardware» more  ISCAS 1995»
15 years 10 months ago
A New Paradigm for Developing Digital Systems Based on a Multi-Cellular Organization
Embryological electronics or “Embryonics” is a new paradigm for developing digital systems of any complexity, endowed of universal computation, self-repair and self-reproducti...
Daniel Mange, Serge Durand, Eduardo Sanchez, Andr&...