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MICRO
2003
IEEE
152views Hardware» more  MICRO 2003»
16 years 6 days ago
A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor
Single-event upsets from particle strikes have become a key challenge in microprocessor design. Techniques to deal with these transient faults exist, but come at a cost. Designers...
Shubhendu S. Mukherjee, Christopher T. Weaver, Joe...
ISLPED
2003
ACM
91views Hardware» more  ISLPED 2003»
16 years 6 days ago
Reducing reorder buffer complexity through selective operand caching
Modern superscalar processors implement precise interrupts by using the Reorder Buffer (ROB). In some microarchitectures , such as the Intel P6, the ROB also serves as a repositor...
Gurhan Kucuk, Dmitry Ponomarev, Oguz Ergin, Kanad ...
WAIFI
2010
Springer
192views Mathematics» more  WAIFI 2010»
16 years 3 hour ago
Type-II Optimal Polynomial Bases
In the 1990s and early 2000s several papers investigated the relative merits of polynomial-basis and normal-basis computations for F2n . Even for particularly squaring-friendly app...
Daniel J. Bernstein, Tanja Lange
CLUSTER
2002
IEEE
15 years 12 months ago
I/O Analysis and Optimization for an AMR Cosmology Application
In this paper, we investigate the data access patterns and file I/O behaviors of a production cosmology application that uses the adaptive mesh refinement (AMR) technique for it...
Jianwei Li, Wei-keng Liao, Alok N. Choudhary, Vale...
IEEEMSP
2002
IEEE
125views Multimedia» more  IEEEMSP 2002»
15 years 12 months ago
Wireless multimedia error resilience via a data hiding technique
Abstract—Transmission of digital contents in unavoidable noiseprone environments demands sophisticated error detection and concealment techniques to restore the perceptual qualit...
Chun-Shien Lu