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ISCAS
2006
IEEE
157views Hardware» more  ISCAS 2006»
16 years 1 months ago
DCOS: cache embedded switch architecture for distributed shared memory multiprocessor SoCs
Abstract— Shared memory is a common inter-processor communication paradigm for on-chip multiprocessor SoC (MPSoC) platforms. The latency overhead of switch-based interconnection ...
Daewook Kim, Manho Kim, Gerald E. Sobelman
ISCAS
2006
IEEE
120views Hardware» more  ISCAS 2006»
16 years 1 months ago
Fast bit permutation unit for media enhanced microprocessors
— Bit and subword permutations are useful in many multimedia and cryptographic applications. New shift and permute instructions have been added to the instruction set of general-...
Giorgos Dimitrakopoulos, Christos Mavrokefalidis, ...
ISCAS
2006
IEEE
93views Hardware» more  ISCAS 2006»
16 years 1 months ago
Radial distribution power flow studies in a remotely distributed environment
—With the continued push toward dispersed generation and distributed intelligent devices throughout the distribution system, a proper analysis method for understanding the operat...
Michael Kleinberg, Karen Miu, Chika O. Nwankpa
ISCAS
2006
IEEE
119views Hardware» more  ISCAS 2006»
16 years 1 months ago
Using self-organizing maps to control physical robots with omnidirectional drives
— In many application areas, robots most suitably employ classical PID controllers and the like. In the field of autonomous mobile robots, however, further adaptation features a...
Ralf Salomon, Hagen Burchardt, T. Schulz
ISCAS
2006
IEEE
100views Hardware» more  ISCAS 2006»
16 years 1 months ago
Decoders for low-density parity-check convolutional codes with large memory
— Low-density parity-check convolutional codes offer the same good error-correcting performance as low-density parity-check block codes while having the ability to encode and dec...
Stephen Bates, L. Gunthorpe, Ali Emre Pusane, Zhen...
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