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IPPS
2005
IEEE
16 years 16 days ago
Technology-based Architectural Analysis of Operand Bypass Networks for Efficient Operand Transport
As semiconductor feature sizes decrease, interconnect delay is becoming a dominant component of processor cycle times. This creates a critical need to shift microarchitectural des...
Hongkyu Kim, D. Scott Wills, Linda M. Wills
165
Voted
MICRO
2005
IEEE
145views Hardware» more  MICRO 2005»
16 years 16 days ago
A Mechanism for Online Diagnosis of Hard Faults in Microprocessors
We develop a microprocessor design that tolerates hard faults, including fabrication defects and in-field faults, by leveraging existing microprocessor redundancy. To do this, we...
Fred A. Bower, Daniel J. Sorin, Sule Ozev
ISLPED
2005
ACM
111views Hardware» more  ISLPED 2005»
16 years 15 days ago
Peak temperature control and leakage reduction during binding in high level synthesis
Temperature is becoming a first rate design criterion in ASICs due to its negative impact on leakage power, reliability, performance, and packaging cost. Incorporating awareness o...
Rajarshi Mukherjee, Seda Ogrenci Memik, Gokhan Mem...
IPPS
2000
IEEE
15 years 11 months ago
Register Assignment for Software Pipelining with Partitioned Register Banks
Many techniques for increasing the amount of instruction-level parallelism (ILP) put increased pressure on the registers inside a CPU. These techniques allow for more operations t...
Jason Hiser, Steve Carr, Philip H. Sweany, Steven ...
222
Voted
ISSS
1999
IEEE
168views Hardware» more  ISSS 1999»
15 years 11 months ago
Automatic Architectural Synthesis of VLIW and EPIC Processors
This paper describes a mechanism for automatic design and synthesis of very long instruction word (VLIW), and its generalization, explicitly parallel instruction computing rocesso...
Shail Aditya, B. Ramakrishna Rau, Vinod Kathail